The manufacture of semiconductor integrated circuits entails a multitude of processes including design, manufacture, packing, and test. Testing is divided into functional, parametric, and bum-in methodologies. In each of these regimes,the devices may be tested in wafer, die, or packaged foam. Although packaging is a comparatively expensive step, semiconductor manufacturers often package the devices before testing, that is, prior to ensuring proper device operation. The high cost of packaging devices. coupled with the increased complexity of the device structures has forced manufacturers to test the devices before packaging, in wafer or die foam. By doing so, the probability of packaging non-operational devices is decreased. Further, with the advent of multichip modules, wafer or die level testing is required since the semiconductor device is only one of several components mounted on a multichip carrier.
A fixed probe board for testing semiconductor wafer chips was disclosed by Hasegawa in U.S. Pat. No. 4,567,640 titled FIXED PROBE BOARD. The Hasagawa probe board comprises a plurality of probe needles mounted to a Support base. The configuration of the probe needles matches an array of pads (for example, pads for data input/output, pads for control signals, pads for addresses, and pads for command) of the integrated circuit to be tested. The probe board disclosed in the '640 patent is impractical for parallel testing plural semiconductor integrated circuits (for example, integrated circuits arranged in an identical row or column) in die or wafer form (hereinafter, referred to as "parallel test").
The parallel test is limited by the number of probe needles that are assigned to each of semiconductor integrated circuits under simultaneous test. This is because probe needles of a probe card (corresponding to the probe board) must be arranged within an area of a memory device under test without being arranged within an area of an adjacent memory device. It becomes difficult to allot the probe needles of the probe card so as to correspond to pads of a tested memory device, particularly data input/output pads (hereinafter, referred to as DQ pads). The number of probe needles allotted to a single device is reduced as the number of devices tested simultaneously. Conversely, as more devices are simultaneously tested, fewer needles are assigned to test a single device.
The parallel test at a wafer level is performed as follows. First, the DQ pads of the device under test, e.g., a memory device, are divided into a plurality of groups. A probe needle is assigned to a single DQ pad in each group. The selected DQ pad is termed a representative DQ pad. Data is then written via the representative DQ pads of each of the semiconductor integrated circuit memory devices under simultaneous test. At this time, data inputted via the representative DQ pad is commonly provided into tile other DQ pads. Data bits are read out from memory cells of the respective memory devices under test. Data bits, corresponding to each group, for example, two data bits, are compared to determine whether the bits have the same logic state. The result of the comparison is outputted via the representative DQ pad. The result of the comparison determines whether memory cells are present or absent, that is, normal or defective. respectively.
The above-described test scheme has the following disadvantage. Where all logic states of data bits corresponding to DQ pads of a group are inverted, it is impossible to determine defective memory cells corresponding to the DQ pads of the group. This is because all the data bits corresponding to the DQ pads of the group have the same logic states. This problem becomes more serious as the number of DQ pads (for example, DQ pads corresponding to the bit organization, x16, x32, x64, etc.) integrated in the memory device increases.